AMD announces 128-bit (GPU-oriented?) SSE5 extensions to x86

AMD announces 128-bit (GPU-oriented?) SSE5 extensions to x86: "EE5 also features new instructions for fused multiply-accumulate, integer multiply-accumulate, compare and test, permutation and conditional move, and precision control, rounding, and conversion. Some of these new instructions work with a new 16-bit floating-point format that SSE5 introduces. This 'half-precision' floating-point format is popular in GPUs, so this format and related instructions are likely intended for AMD's forthcoming 'Fusion' product. All told, SSE5 adds over 100 new instructions (base instructions plus variants) to the x86 ISA. No doubt AMD hopes to repeat history here—x86-64 history, not 3DNow! history—by getting Intel to eventually adopt the extensions. However, my (still fairly preliminary) reading of Intel's QuickAssist technology suggests that Intel will take a different approach to integrating many-core, GPU-style acceleration with the x86 ISA. More on this at a later time, though."