AMD IBS

http://developer.amd.com/Assets/AMD_IBS_paper_EN.pdf
Instruction-Based Sampling is a feature introduced in AMD Family 10h processors. Although IBS is a statistical method, the sampling technique delivers precise event information and eliminates inaccuracies due to skid.
The processor pipeline has two main phases: instruction fetch and instruction execution. The fetch phase supplies instruction bytes to the decoder. Decoded AMD64 instructions are executed during the execution phase as discrete operations called "ops." Since the two phases are decoupled, IBS provides two forms of sampling: fetch sampling and op sampling. IBS fetch sampling provides information about the fetch phase and IBS op sampling provides information about the execution phase.
IBS fetch sampling and IBS op sampling use a similar sampling technique. The IBS hardware selects an operation periodically based on a configurable sampling period. The selected operation is tagged and the operation is monitored as it proceeds through the pipeline. Events caused by the operation are recorded. When the operation completes, the event information and the fetch (or instruction) address associated with the operation are reported to the profiler. Thus, events are precisely attributed to the instruction that caused them. IBS does not impose any overhead on instruction fetch or execution -- everything runs at full speed.